asahi kasei [AKD4632-a] 2005/04 - 1 - general description AKD4632-a is an evaluatio n board for the ak4632, 16bit mono co dec with mic/spk/video amplifier. the AKD4632-a can evaluate a/d converter and d/a converter separately in addition to loopback mode (a/d d/a). AKD4632-a also has the digital audio inte rface and can achieve the interface with digital audio systems via opt-connector. ? ordering guide AKD4632-a --- evaluation board for ak4632 (cable for connecting with printer port of ibm-at, compatible pc and control software are packed with this. this control software does not support windows nt.) function ? dit/dir with optical input/output ? bnc connector for an external clock input ? 10pin header for serial control mode 10pin header control data 10pin header gnd beep/min/mout ak4114 opt in opt out clock gen ak4632 svdd avdd dsp dvdd vvdd mic-jack spk-jack aout mic vin vout 5v regulator 3.3v figure 1. AKD4632-a block diagram * circuit diagram and pcb layout are attached at the end of this manual. ak4632 evaluation board rev.0 a kd4632- a
asahi kasei [AKD4632-a] 2005/04 - 2 - evaluation board manual ? operation sequence 1) set up the power supply lines. 1-1) when avdd, dvdd, svdd, vvdd and vcc are supplied from the regulator. (avdd, dvdd, svdd, vvdd and vcc jack should be open.). see ? other jumper pins set up (page 10)?. [reg] (red ) = 5v [avdd] (orange) = open : 3.3v is supplied to avdd of ak4632 from regulator. [dvdd] (orange) = open : 3.3v is supplied to dvdd of ak4632 from regulator. [svdd] (blue) = open : 3.3v is supplied to svdd of ak4632 from regulator. [vvdd] (blue) = open : 3.3v is supplied to vvdd of ak4632 from regulator. [vcc] (orenge) = open : 3.3v is supplied to logic block from regulator. [avss] (black) = 0v : for analog ground [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground 1-2) when avdd, dvdd, svdd, vvdd and vcc are not supplied from the regulator. (avdd, dvdd, svdd, vvdd and vcc jack should be junction.) see ? other jumper pins set up (page 10)?. [reg] (red) = ?reg? jack should be open. [avdd] (orange) = 2.6 3.6v : for avdd of ak4632 (typ. 3.3v) [dvdd] (orange) = 2.6 3.6v : for dvdd of ak4632 (typ. 3.3v) [svdd] (blue) = 2.6 5.25v : for svdd of ak4632 (typ. 3.3v, 5.0v) [vvdd] (blue) = 2.6 5.25v : for vvdd of ak4632 (typ. 3.3v, 5.0v) [vcc] (orenge) = 2.6 3.6v : for logic (typ. 3.3v) [avss] (black) = 0v : for analog ground [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground each supply line should be distributed from the power supply unit. avdd and dvdd must be same voltage level. 2) set up the evaluation mode, jumper pins and dip switches. (see the followings.) 3) power on. the ak4632 and ak4114 should be reset once bringing sw1, 2 ?l? upon power-up. ? evaluation mode in case of ak4632 evaluation using ak4114, it is nece ssary to correspond to audio interface format for ak4632 and ak4114. about ak4632?s audi o interface format, refer to datasheet of ak4632. about ak4114?s audio interface format, refer to table 2 in this manual. applicable evaluation mode (1) evaluation of l oop-back mode (a/d d/a) : pll, master mode (default) (2) evaluation of l oop-back mode (a/d d/a) : pll, slave mode (pll reference clock: mcki pin) (3) evaluation of l oop-back mode (a/d d/a) : pll, slave mode (pll reference clock: bick or fck pin) (4) evaluation of using di r of ak4114 (opt-connecto r) : ext, slave mode (5) evaluation of using di t of ak4114 (opt-connect or) : ext, slave mode
asahi kasei [AKD4632-a] 2005/04 - 3 - (1) evaluation of l oop-back mode (a/d d/a) : pll, master mode (default) a) set up jumper pins of mcki clock ?mckpd bit? in the ak4632 should be set to ?0?. x?tal of 11.2896mhz, 12mhz, 12.288mhz, 13mhz, 24mhz or 27mhz can be set in x1. x?tal of 12.288mhz (default) is set on the AKD4632-a. set ?no.8 of sw3? to ?h?. when an external clock (11.2896mhz, 12mhz, 12.288mhz, 13mhz, 24mhz or 27mhz) through a rca connector (j8: ext/bick) is supplied, select ext on jp21 (mclk_sel) and short jp17 (xte). jp23 (ext1) and r26 should be properly selected in order to much the output impedance of the clock generator. b) set up jumper pins of bick clock output frequency (16fs/32fs/64fs) of bick s hould be set by ?bcko1-0 bit? in the ak4632. there is no necessity for set up jp19. c) set up jumper pins of fck clock d) set up jumper pins of data when the ak4632 is evaluated by loop-back mode (a/d d/a), the jumper pins should be set to the following. jp17 xte mclk_sel jp21 jp18 mkfs 256fs 512fs 1024fs xtl dir ext mcko jp6 mcki jp22 fck_sel 2fs ext jp28 fck adc dir 1fs jp26 4632_sdti adc dac/loop jp30 sdti dir adc jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv bick_sel jp19 ext 16fs 32fs 64fs
asahi kasei [AKD4632-a] 2005/04 - 4 - (2) evaluation of loop-back mode (a/d d/a) : pll, slave mode (pll reference clock: mcki pin) a) set up jumper pins of mcki clock ?mckpd bit? in the ak4632 should be set to ?0?. x?tal of 12.288mhz (default) is set on the AKD4632-a. in this case, the ak4632 corresponds to pll reference clock of 12.288mhz. in this evaluation mode, the output clock from mcko-pin of the ak4632 is supplied to a divider (u3: 74vhc4040), bick and fck clocks are generated by the divider. then ?mcko bit? in the ak4632 is set to ?1?. when an external clock through a rca connector (j8: ext/bick) is supplied, select ext on jp21 (mclk_sel) and short jp17 (xte). jp23 (ext1) and r26 should be properly selected in order to much the output impedance of the clock generator. b) set up jumper pins of bick clock c) set up jumper pins of fck clock d) set up jumper pins of data when the ak4632 is evaluated by loop-back mode (a/d d/a), the jumper pins should be set to the following. jp17 xte mclk_sel jp21 jp18 mkfs 256fs 512fs 1024fs xtl dir ext mcko jp6 mcki jp28 fck adc dir jp22 fck_sel 2fs ext 1fs jp26 4632_sdti adc dac/loop jp30 sdti dir adc jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv bick_sel jp19 ext 16fs 32fs 64fs
asahi kasei [AKD4632-a] 2005/04 - 5 - (3) evaluation of loop- back mode (a/d d/a) : pll, slave mode (pll reference clock: bick or fck pin) a) set up jumper pins of mcki clock ?mckpd bit? in the ak4632 should be set to ?1?. jp6 (mcki) should be open. b) set up jumper pins of bick clock when an external clock through a rca connector j8 (ext/bick) is supplied, select ext on jp19 (mclk_sel) and short jp17 (xte). jp23 (ext1) and r26 should be properly selected in order to much the output impedance of the clock generator. in this evaluation mode, the selected clock from jp21 (mclk_sel) is supplied to a divider (u3: 74vhc4040), bick and fck clocks are generated by the divider. input frequency of master clock is set up in turn ?256fs?, ?512fs?, ?1024fs? from left. and input frequency of bick is set up in turn ?16fs?, ?32fs?, ?64fs? from left. jp17 xte mclk_sel jp21 xtl dir ext jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv jp18 mkfs 256fs 512fs 1024fs mcko jp18 mkfs 256fs 512fs 1024fs mcko jp18 mkfs 256fs 512fs 1024fs mcko bick_sel jp19 ext 16fs 32fs 64fs bick_sel jp19 ext 16fs 32fs 64fs bick_sel jp19 ext 16fs 32fs 64fs
asahi kasei [AKD4632-a] 2005/04 - 6 - c) set up jumper pins of fck clock when an external clock through a rca connector j9 (fck) is supplied, select ext on jp22 (fck_sel). jp24 (ext2) and r27 should be properly selected in order to much the output impedance of the clock generator. d) set up jumper pins of data when the ak4632 is evaluated by loop-back mode (a/d d/a), the jumper pins should be set to the following. jp28 fck adc dir jp22 fck_sel 2fs ext 1fs jp26 4632_sdti adc dac/loop jp30 sdti dir adc
asahi kasei [AKD4632-a] 2005/04 - 7 - (4) evaluation of using dir of ak41 14 (opt-connector) : ext, slave mode a) set up jumper pins of mcki clock ?mckpd bit? in the ak4632 should be set to ?0?. b) set up jumper pins of bick clock c) set up jumper pins of fck clock jp24 (ext2) and r27 should be properly selected in order to much the output impedance of the clock generator. d) set up jumper pins of data when d/a converter of the ak4632 is evaluated by using dir of ak4114, the jumper pins should be set to the following. jp17 xte mclk_sel jp21 xtl dir ext jp6 mcki jp18 mkfs 256fs 512fs 1024fs jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv bick_sel jp19 ext 16fs 32fs 64fs jp28 fck adc dir jp22 fck_sel 2fs ext 1fs jp26 4632_sdti adc dac/loop jp30 sdti dir adc
asahi kasei [AKD4632-a] 2005/04 - 8 - (5) evaluation of using dit of ak4114 (opt-c onnector) : ext, slave mode a) set up jumper pins of mcki clock ?mckpd bit? in the ak4632 should be set to ?0?. b) set up jumper pins of bick clock c) set up jumper pins of fck clock jp24 (ext2) and r27 should be properly selected in order to much the output impedance of the clock generator. d) set up jumper pins of data when a/d converter of the ak4632 is evaluated by using dir of ak4114, the jumper pins should be set to the following. jp17 xte mclk_sel jp21 xtl dir ext jp6 mcki jp18 mkfs 256fs 512fs 1024fs jp28 fck adc dir jp22 fck_sel 2fs ext 1fs jp26 4632_sdti adc dac/loop jp30 sdti dir adc jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv bick_sel jp19 ext 16fs 32fs 64fs
asahi kasei [AKD4632-a] 2005/04 - 9 - ? dip switch set up [sw3] (mode) : mode setting of ak4632 and ak4114 on is ?h?, off is ?l?. no. name on (?h?) off (?l?) 1 dif0 2 dif1 3 cm2 ak4114 audio format setting see table 2 4 cm0 5 cm1 clock operation mode select see table 3 6 ocks0 7 ocks1 master clock frequency select see table 4 8 m/s master mode slave mode note. when the ak4632 is evaluated master mode, ?no.8 of sw3? is set to ?h?. table 1. mode setting for ak4632 and ak4114 register setting for ak4632 audio interface format setting for ak4114 audio interface format dif1 bit dif0 bit dif0 dif1 dif2 daux sdto 0 1 l l l 24bit, left justified 16bit, right justified 1 0 l l h 24bit, left justified 24bit, left justified default 1 1 h l h 24bit, i 2 s 24bit, i 2 s note. when the ak4632 is evaluated by using dir/dit of ak4114, ?no.8 of sw3? is set to ?l?. table 2. setting for ak4114 audio interface format mode cm1 cm0 unlock pll x'tal clock source sdto 0 0 0 - on on(note) pll rx 1 0 1 - off on x'tal daux 0 on on pll rx 2 1 0 1 on on x'tal daux default 3 1 1 - on on x'tal daux on: oscillation (power-up), off: stop (power-down) note : when the x?tal is not used as clock comparison fo r fs detection (i.e. xtl1,0= ?1,1?), the x?tal is off. table 3. clock operation mode select no. ocks1 mcko1 mcko2 x?tal 0 0 256fs 256fs 256fs 2 1 512fs 256fs 512fs default table 4. master clock frequency select (stereo mode)
asahi kasei [AKD4632-a] 2005/04 - 10 - ? other jumper pins set up 1. jp1 (gnd) : analog ground and digital ground open : separated. short : common. (the connector ?dgnd? can be open.) 2. jp2 (ain) : connection between micout pin and ain pin of the ak4632. open : no connection. short : connection. 3. jp3 (avdd_sel) : avdd of the ak4632 reg : avdd is supplied from the regulator (?avdd? jack should be open). < default > avdd : avdd is supplied from ?avdd ? jack. 4. jp8 (vvdd_sel) : vvdd of the ak4632 avdd : avdd is supplied from ?avdd?. < default > vvdd : vvdd is supplied from ?vvdd ? jack. 5. jp9 (dvdd_sel) : dvdd of the ak4632 avdd : dvdd is supplied from ?avdd?. < default > dvdd : dvdd is supplied from ?dvdd ? jack. 6. jp10 (lvc_sel) : logic block of lvc is selected supply line. dvdd : logic block of lvc is supplied from ?dvdd?. < default > vcc : logic block of lvc is supplied from ?vcc ? jack. 7. jp11 (vcc_sel) : logic block is selected supply line. lvc : logic is supplied from supply line of lvc. < default > vcc : logic block of lvc is supplied from ?vcc ? jack. 8. jp4 (svdd_sel) : svdd of the ak4632 reg : svdd is supplied from the regulator (?svdd? jack should be open). < default > svdd : svdd is supplied from ?svdd ? jack. 9. jp8 (mcko_sel) : master clock frequency is selected clock from mcko1 or mcko2 of the ak4114. mcko1 : the check from mcko1 of ak4114 is provided to mcki of the ak4632. < default > mcko2 : the check from mcko2 of ak4114 is provided to mcki of the ak4632.
asahi kasei [AKD4632-a] 2005/04 - 11 - ? the function of the toggle sw [sw1] (dir) : power control of ak4114. keep ?h? during normal operation. keep ?l? when ak4114 is not used. [sw2] (pdn) : power control of ak4632. keep ?h? during normal operation. ? indication for led [led1] (erf): monitor int0 pin of the ak4114. led turns on when some error has occurred to ak4114. ? serial control the ak4632 can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port2 (ctrl) with pc by 10 wire flat cable packed with the AKD4632-a connect csn cclk cdti 10pin header 10pin connector 10 wire flat cable pc AKD4632 figure 2. connect of 10 wire flat cable
asahi kasei [AKD4632-a] 2005/04 - 12 - ? analog input / output circuits (1) input circuits a) mic input circuit figure 3. mic input circuit (a-1) analog signal is input to int pin via j1 connector. jp12 mic_sel jack rca (a-2) analog signal is input to int pin via j3 connector. jp12 mic_sel jack rca b) vin input circuit figure 4. vin input circuit j3 mr-552ls avss avss jack 1 jp12 mic_sel int mic 3 rca j1 mic- ja ck 6 4 3 2 j6 mr-552ls avss c29 0.1u r23 75 vin vin 2 3 1 avss
asahi kasei [AKD4632-a] 2005/04 - 13 - (2) output circuits a) aout output circuit figure 5. aout output circuit b) vout output circuit figure 6. vout output circuit (b-1) ?dc output? is output from j7 connector. jp5 vout_sel 11 00 jp7 vsag_sel 11 00 (b-2) ?sag trimming circuit ? is output from j7 connector. jp5 vout_sel 11 00 jp7 vsag_sel 11 00 j5 mr-552ls aout r20 220 2 1 3 r21 20k + c28 1u 1 2 avss avss aout j7 mr-552ls 00 2 11 11 r41 100k vsag jp5 vout_sel + c18 1u 1 2 avss 00 vout r22 75 + c17 47u 1 2 3 jp7 vsag_sel 1 vout avss
asahi kasei [AKD4632-a] 2005/04 - 14 - c) spk output circuit note. when mini-jack is inserted or pulled out j2 (spk-jack) connector, jp13 (spp_sel) and jp14 (spn_sel) should be open, or ?pmspk bit? in the ak4632 should be set to ?0?. figure 7. spk output circuit (c-1) ?dynamic speaker? of external is evaluated by using j2 (spk-jack) connector. (c-2) ?piezo (ceramic) speaker? of external is evaluated by using j2 (spk-jack) connector. spp jp13 spp_sel spk1 dy namic d2 diode z ener a k jp14 spn_sel pie z o ( ext) dy namic ( ext) 020s16 svss r r15 10 pie z o ( ext) l r17 10 d1 diode z ener a k jp31 dy namic cn5 1 2 dy namic svss j2 spk-jack 6 4 3 dy namic ( ext) spn svss jp14 spn_sel dynamic dynamic(ext) piezo(ext) jp13 spp_sel dynamic dynamic(ext) piezo(ext) jp31 dynamic jp14 spn_sel dynamic dynamic(ext) piezo(ext) jp13 spp_sel dynamic dynamic(ext) piezo(ext) jp31 dynamic
asahi kasei [AKD4632-a] 2005/04 - 15 - (c-3) analog signal of spp/spn pins are output ?dynamic speaker? on the evaluation (spk1). (3) beep/min/mout input and output circuit figure 8. beep/min/mout input and output circuit (3-1) analog signal is input to min pin from j4 connector. jp15 min/mout out in jp16 beep/min/mout mout min beep (3-2) analog signal of mout pin is output from j4 connector. jp15 min/mout out in jp16 beep/min/mout mout min beep jp14 spn_sel dynamic dynamic(ext) piezo(ext) jp13 spp_sel dynamic dynamic(ext) piezo(ext) jp31 dynamic j4 mr-552ls beep/ min/ mout + c24 1u 1 2 min r18 47k out r16 20k jp16 beep/ min/ mout in beep beep jp15 min/ mout min mout avss + c26 1u 1 2 r19 20k 1 avss 3 avss c25 0.1u mout 2
asahi kasei [AKD4632-a] 2005/04 - 16 - (3-3) analog signal of mout pin is input to min pin. jp15 min/mout out in jp16 beep/min/mout mout min beep (3-4) analog signal is input to beep pin from j4 connector. jp15 min/mout out in jp16 beep/min/mout mout min beep ? akm assumes no responsibility for the trouble when using the above circuit examples.
asahi kasei [AKD4632-a] 2005/04 - 17 - control software manual ? set-up of evaluation board and control software 1. set up the AKD4632-a according to previous term. 2. connect ibm-at compatible pc with AKD4632-a by 10-line type flat cable (packed with AKD4632-a). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not needed. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?AKD4632-a evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?AKD4632.exe? to set up the control program. 5. then please evaluate according to the follows. ? operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port reset? button. 3. click ?write default? button ? explanation of each buttons 1. [port reset] : set up the usb interface board (akdusbif-a) when using the board. 2. [write default] : initialize the register of the ak4632. 3. [all write] : write all registers that is currently displayed. 4. [function1] : dialog to write data by keyboard operation. 5. [function2] : dialog to write data by keyboard operation. 6. [function3] : the sequence of register setting can be set and executed. 7. [function4] : the sequence that is created on [function3] can be assigned to buttons and executed. 8. [function5]: the register setting that is created by [save] function on main window can be assigned to buttons and executed. 9. [save] : save the current register setting. 10. [open] : write the saved values to all register. 11. [write] : dialog to write data by mouse operation. ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
asahi kasei [AKD4632-a] 2005/04 - 18 - ? explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corresponding to each register. click the [write] button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to the ak4632, click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexadecimal. if you want to write the input data to the ak4632, click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate datt there are dialogs corresponding to register of 09h and 0ah. address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is written to the ak4632 by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not return to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to the ak4632, click [ok] button. if not, click [cancel] button.
asahi kasei [AKD4632-a] 2005/04 - 19 - 4. [save] and [open] 4-1. [save] all of current register setting values displayed on the main window are saved to the file. the extension of file name is ?akr?. (1) click [save] button. (2) set the file name and click [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting values saved by [save] are written to the ak4632. the file type is the same as [save]. (1) click [open] button. (2) select the file (*.akr) and click [open] button.
asahi kasei [AKD4632-a] 2005/04 - 20 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. (2) set the control sequence. set the address, data and interval time. set ?-1? to the address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 1. window of [f3]
asahi kasei [AKD4632-a] 2005/04 - 21 - 6. [function4 dialog] the sequence file (*.aks) saved by [function3] can be listed up to 10 files, assigned to buttons and then executed. when [f4] button is clicked, the window as shown in figure 2 opens. figure 2. [f4] window
asahi kasei [AKD4632-a] 2005/04 - 22 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the sequence file (*.aks) saved by [function3]. the sequence file name is displayed as shown in figure 3. ( in case that the selected sequence file name is ?dac_stereo_on.aks?) figure 3. [f4] window(2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save] : the name assign of sequence file displayed on [function4] window can be saved to the file. the file name is ?*.ak4?. [open] : the name assign of sequence file(*.ak4) saved by [save] is loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files used by [save] and [open] function on right side need to be in the same folder. (3) when the sequence is changed in [function3], the sequence file (*.aks) should be loaded again in order to reflect the change.
asahi kasei [AKD4632-a] 2005/04 - 23 - 7. [function5 dialog] the register setting file(*.akr) saved by [save] function on main window can be listed up to 10 files, assigned to buttons and then executed. when [f5] button is clicked, the window as shown in figure 4 opens. figure 4. [f5] window 7-1. [open] buttons on left side and [write] button (1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 5. (in case that the selected file name is ?dac_output.akr?) (2) click [write] button, then the register setting is executed.
asahi kasei [AKD4632-a] 2005/04 - 24 - figure 5. [f5] windows(2) 7-2. [save] and [open] buttons on right side [save] : the name assign of register setting file displayed on [function5] window can be saved to the file. the file name is ?*.ak5?. [open] : the name assign of register setting file(*.ak5) saved by [save] is loaded. 7-3. note (1) all files used by [save] and [open] function on right side need to be in the same folder. (2) when the register setting is changed by [save] button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
asahi kasei [AKD4632-a] 2005/04 - 25 - measurement results example 1.ak4632 mode: ex t mode (slave) [measurement condition] ? measurement unit: rohde & schwarz, upd05 ? mcki: 256fs, 512fs ? bick: 64fs ? bit: 16bit ? sampling frequency: 8khz & 16khz ? measurement frequency: 20 3.4khz (fs=8khz), 20 8khz (fs=16khz) ? power supply: avdd=dvdd=vvdd=3.3v,svdd=3.3v/5.0v ? temperature: room ? input frequency: 1khz [measurement results] 1.adc characteristics (mic gain = +20db, ipga=0db, alc1 = off, mic ? ipga ? adc) result mcki clock 512fs 256fs sampling frequency 8khz 16khz 8khz 16khz s/(n+d) (-1dbfs) 84.3db 84.1db 84.4db 84.0db d-range (-60dbfs) 88.1db 86.4db 85.2db 86.3db s/n 88.1db 86.3db 88.2db 86.3db 2. dac characteristics (aout) (dac ? aout, dvol = 0db) result mcki clock 512fs 256fs sampling frequency 8khz 16khz 8khz 16khz s/(n+d) (0dbfs) 91.5db 89.6db 90.8db 89.5db d-range (-60dbfs) 94.8db 92.0db 94.5db 92.1db s/n 95.5db 93.5db 95.0db 93.5db 3. speaker-amp characteristics (dac ? mout ? min ? spp/spn, alc2=off) result spkg1-0 = ?00? (-0.5dbfs) 69.6db svdd=3.3v rl=8 ? spkg1-0 = ?01? (-0.5dbfs) 73.5db spkg1-0 = ?10? (-0.5dbfs) 73.2db s/(n+d) svdd=5.0v rl=10 ? , cl=3uf spkg1-0 = ?11? (-0.5dbfs) 73.8db spkg1-0 = ?00? 90.4db svdd=3.3v rl=8 ? spkg1-0 = ?01? 91.7db spkg1-0 = ?10? 90.6db s/n svdd=5.0v rl=10 ? , cl=3uf spkg1-0 = ?11? 91.0db 4. loop-back (mic ? adc ? dac ? aout) result mcki clock 512fs 256fs sampling frequency 8khz 16khz 8khz 16khz s/(n+d) (-1dbfs) 84.2db 83.2db 84.2db 83.4db d-range (-60dbfs) 88.4db 85.9db 87.0db 85.9db s/n 88.4db 86.0db 87.0db 86.0db
asahi kasei [AKD4632-a] 2005/04 - 26 - 2.ak4632 mode: pll slave mode [measurement condition] ? measurement unit: rohde & schwarz, upd05 ? bit: 16bit ? sampling frequency: 8khz & 16khz ? measurement frequency: 20 3.4khz (fs=8khz), 20 8khz (fs=16khz) ? power supply: avdd=dvdd=svdd=vvdd=3.3v ? temperature: room ? input frequency: 1khz [measurement results] 2-1. pll reference clock : bick or fck pin loop-back (mic ? adc ? dac ? aout) result pll reference clock 1fs (fck pin) 16fs (bick pin) sampling frequency 8khz 16khz 8khz 16khz s/(n+d) (-1dbfs) 75.3db 78.6db 84.7db 83.8db d-range (-60dbfs) 86.5db 86.0db 87.7db 85.9db s/n 86.5db 85.9db 87.6db 85.8db 2-2. pll reference clock : mcki pin loop-back (mic ? adc ? dac ? aout) result pll reference clock 12.288mhz sampling frequency 8khz 16khz s/(n+d) (-1dbfs) 84.7db 83.8db d-range (-60dbfs) 87.4db 85.8db s/n 88.0db 85.8db 3.ak4632 mode: pll master mode [measurement condition] ? measurement unit: rohde & schwarz, upd05 ? mcki: 12.288mhz ? bick: 16fs ? bit: 16bit ? sampling frequency: 8khz & 16khz ? measurement frequency: 20 3.4khz (fs=8khz), 20 8khz (fs=16khz) ? power supply: avdd=dvdd=svdd=vvdd=3.3v ? temperature: room ? input frequency: 1khz [measurement results] loop-back (mic ? adc ? dac ? aout) result 8khz 16khz s/(n+d) (-1dbfs) 84.2db 83.3db d-range (-60dbfs) 86.9db 85.0db s/n 87.0db 85.0db
asahi kasei [AKD4632-a] 2005/04 - 27 - 4.plot data (ext slave mode) 4-1.adc (mic ? adc) plot data figure 1. thd+n vs. input level figure 2. thd+n vs. input frequency (input level = -1dbfs), c7: ceramic condenser in this case, a ceramic condenser is used as c7 between micout pin as ain pin on the AKD4632-a.as the performance of ceramic condenser is not so good about low frequency signal. refer to figure 3 about the performance of ak4632.
asahi kasei [AKD4632-a] 2005/04 - 28 - figure 3. thd+n vs. input frequency (input level = -1dbfs), c7: film condenser figure 4. linearity
asahi kasei [AKD4632-a] 2005/04 - 29 - figure 5. frequency response (by the board of AKD4632-a) high pass filter is composed by the input impedance of ai n pin and c7 between micout pin and ain pin. refer to figure 6 about frequency response of ak4632?s adc. figure 6. frequency response (ain ? adc)
asahi kasei [AKD4632-a] 2005/04 - 30 - figure 7. fft plot ( input level=-1.0dbfs) figure 8. fft plot ( input level=-60.0dbfs )
asahi kasei [AKD4632-a] 2005/04 - 31 - figure 9. fft plot ( ?0? data input )
asahi kasei [AKD4632-a] 2005/04 - 32 - 4-2. dac (dac ? aout) plot data figure 10. thd+n vs. input level figure 11. thd+n vs. input frequency (input level = 0dbfs)
asahi kasei [AKD4632-a] 2005/04 - 33 - figure 12. linearity figure 13. frequency response
asahi kasei [AKD4632-a] 2005/04 - 34 - figure 14. fft plot ( input level=0dbfs ) figure 15. fft plot ( input level=-60.0dbfs )
asahi kasei [AKD4632-a] 2005/04 - 35 - figure 16. fft plot ( ?0? data input )
asahi kasei [AKD4632-a] 2005/04 - 36 - 4-3. video plot data [measurement condition] ? measurement unit: tektronix vm700t video measurement set ? power supply: avdd=dvdd=svdd=3.3v,vvdd=3.3v ? temperature: room ? input frequency: 1khz 4-3-1. s/n ? measurement frequency: 100kh 6mhz figure 1. noise spectrum
asahi kasei [AKD4632-a] 2005/04 - 37 - 4-3-2. sag figure 2. field time distortion (dc output, sagc bits = ?00?) figure 3. field time distortion (sag trimming 47 f+ 1.0uf, sagc bits = ?10?)
asahi kasei [AKD4632-a] 2005/04 - 38 - figure 4. field time distortion (sag trimming 100 f+ 2.2uf, sagc bits = ?11?) 4-3-3. vector ? input signal: 75% color figure 5. 75% color vector (sag trimming 47 f+ 1.0uf, sagc bits = ?10?)
asahi kasei [AKD4632-a] 2005/04 - 39 - revision history date manual revision board revision reason contents 04/11/24 km075601 0 first edition 05/04/05 km075602 0 change ?control software manual? chapter is changed by version up of control software. important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulati ons of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributo r of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
a a b b c c d d e e e e d d c c b b a a reg svd d reg avdd avss av ss av ss avss svs s svs s avss av ss svss avss vvdd avdd av ss dvdd av ss avdd avss av ss avss svss vcc dvd d lvc vcc sagc0 0 sagc1 1 sagc0 0 sagc1 1 av ss svs s ak4632 0 akd 4632 a3 1 5 wednesday, august 18, 20 04 title size document number rev date: sheet of 4632_m cki int mout 4632_sd to spp beep spn cc lk 463 2_fck ao ut min avdd vi n 463 2_bick dv dd cdti reg reg reg 46 32_mcko vou t pdn csn 4632_s dti avd d avd d dvd d lvc d3. 3v svd d re g_in avdd vvdd dvdd vcc(3.3v ) re g_in avd d dvdd vvd d sv dd r1 2.2k jp5 vou t_sel t1 ta4803 3f in out gnd u1 ak4632 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 12 24 25 vcoc avdd avss vvdd vin vout vsag pdn csn cclk cdti sdto fck bick dvdd dvss mcki mcko spn spp svdd svss aout beep ain micout mic mpi vcom sdti min mout c2 0 0.1 u + c1 8 1u 1 2 r1 2 470 r1 1 51 + c9 10u 1 2 vvd d t45_b u 1 r4 0 (short) l2 (short) 1 2 + c2 2 47 u 1 2 jp9 dvdd_sel cn1 32 pin_4 25 26 27 28 29 30 31 32 jp6 mcki + c1 2 10u 1 2 r2 10k + c1 9 47 u 1 2 jp8 vvdd_s el + c4 2.2 u 1 2 r1 4 10 c1 5 0.1 u jp1 gnd jp2 ain svs s t45 _bk 1 c2 0. 1u r4 (op en) c8 4.7 n r8 51 jp4 svd d_sel cn4 32 pin_2 9 10 11 12 13 14 15 16 c7 0.2 2u r9 51 c5 0. 1u r5 (short) l3 (short) 1 2 jp7 vsa g_sel + c2 3 47 u 1 2 reg t45_r 1 sv dd t45_b u 1 r3 (short) r1 3 470 jp10 lvc_ sel cn2 32p in_1 1 2 3 4 5 6 7 8 l5 (short) 1 2 + c2 1 10 u 1 2 r1 0 51 c1 0. 1u l4 (short) 1 2 + c1 7 47 u 1 2 avss t45 _bk 1 dvdd t4 5_o 1 cn3 32 pin_3 17 18 19 20 21 22 23 24 + c1 4 10u 1 2 + c3 47 u 1 2 + c1 3 47 u 1 2 l1 (short) 1 2 + c1 6 47 u 1 2 + c6 1u 1 2 r6 51 jp3 avdd_s el c1 1 0.1 u jp11 vcc_sel dgnd t45_ bk 1 avd d t4 5_o 1 c1 0 0.1 u r7 51
a a b b c c d d e e e e d d c c b b a a in out jac k av ss avss av ss avss av ss avss 2 3 mic 1 rca beep/mi n/mout 2 3 1 avss mout min beep l r 02 0s16 spk1 svss dynami c(ext) dy namic piez o(ext) svss dynami c(ext) piez o(ext) dy namic 3 1 2 aou t avss 1 3 2 vin avss 2 avss 1 3 vou t svs s av ss input/output 0 akd 4632 a3 2 5 wednesday, august 18, 20 04 title size document number rev date: sheet of mout spn spp int aou t min beep vin vou t jp15 min/mo ut jp12 mi c_sel r1 8 47k j7 mr-55 2ls r2 3 75 r2 1 20k c2 9 0. 1u j3 mr-552 ls + c2 6 1u 1 2 j6 mr-552 ls j4 mr-552 ls r1 5 10 jp16 beep/min /mout d1 diode zener a k r2 0 22 0 c2 5 0.1 u jp13 spp_sel r1 7 10 r4 1 100 k r2 2 75 j2 spk-j ack 6 4 3 r1 9 20 k jp31 dy namic + c2 4 1u 1 2 j5 mr-55 2ls jp14 sp n_sel j1 mic -jack 6 4 3 r1 6 20k d2 diode zener a k cn5 1 2 + c2 8 1u 1 2
a a b b c c d d e e e e d d c c b b a a ext 10 24fs 64f s 512 fs 256 fs 32f s inv thr 16f s 1fs xtl ext ext for 74hcu04,74ac74,74vhc4040,74hc14,74hc14,74hc541,74hct04 mcko dir 3 1 ext/b ick av ss 2 2 fck 1 3 av ss 2fs clock 0 akd 4632 a3 3 5 wednesday, august 18, 20 04 title size document number rev date: sheet of ex t_mclk ext_ bick mcko dir_mcl k ext _fck d3 .3v vcc vcc u4a 74 ac74 2 3 5 6 4 1 d clk q q pr cl jp18 mkfs c3 3 0.1 u r2 6 51 r2 7 51 c3 4 0.1 u jp22 fck_s el j8 mr-55 2ls r2 5 shor t u5a 74hc14 1 2 r2 4 1m u2a 74hcu0 4 1 2 x1 12.28 8mhz 1 2 u2b 74hcu0 4 3 4 u4b 74 ac74 12 11 9 8 10 13 d clk q q pr cl c3 6 0.1 u c3 5 0.1 u jp17 xt e c3 1 0.1 u + c3 7 47 u 1 2 j9 mr-55 2ls jp23 ext1 c3 9 (op en) c3 0 0.1 u u3 74vhc404 0 10 11 9 7 6 5 3 2 4 13 12 14 15 1 clk rst q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 c3 8 (op en) jp20 bick c3 2 0.1 u jp19 bick_s el jp24 ext2 jp21 mclk_se l
a a b b c c d d e e e e d d c c b b a a h l dif0 dif2 cm0 ock s1 m/ s cm1 dif1 ock s0 mc ko2 mc ko1 dir/dit 0 akd 4632 a3 4 5 wednesday, august 18, 20 04 title size document number rev date: sheet of da ux dir_sd ti dir _bick dir_fck cm0 cm0 d3. 3v d3. 3v cm1 ock s0 cm1 ock s1 d3. 3v d3. 3v m/s d3. 3v d3. 3v d3. 3v ock s1 ock s0 dir_mcl k + c4 3 10u 1 2 c4 1 0. 1u c4 6 0.4 7u u6 ak4114 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 12 24 25 37 ips0 nc dif0 test2 dif1 nc dif2 ips1 p/sn xtl0 xtl1 tvdd dvss tx0 tx1 bout cout uout vout dvdd dvss mcko1 bick mcko2 daux xto xti pdn cm0 cm1 ocks1 ocks0 int0 avdd r vcom avss rx0 nc rx1 test1 rx2 nc rx3 vin lrck sdto int1 c4 4 0. 1u + c5 1 10 u 1 2 u5c 74hc14 5 6 d3 hsu11 9 k a c4 9 0.1 u c5 3 0.1 u c4 8 (op en) + c5 2 10 u 1 2 u7a 74 hc04 1 2 c5 0 0.1 u c4 7 (op en) c4 5 0.1 u sw 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r3 1 1k u5b 74hc14 3 4 r2 9 470 x2 11.2896 mhz 1 2 c4 2 0. 1u led1 erf k a r3 0 18 k r2 8 10k jp25 mcko_ sel c4 0 0.1 u sw 1 dir 2 1 3 port1 to rx141 1 3 2 out vcc gnd port2 tot x141 1 2 3 gnd vcc in l6 (short) 1 2 rp1 47k 1 2 3 4 5 6 7 8 9
a a b b c c d d e e e e d d c c b b a a fck ad c adc dir mcl k vcc sdti dir bick ccl k cdti csn l h ad c dir inv thr dac/ loop adc logic 0 akd 4632 a3 5 5 wednesday, august 18, 20 04 title size document number rev date: sheet of 463 2_sdti 4632_ mcki da ux 4632_fck 4632_bic k lvc da ux ext_ bick dir_sd ti 4632_m cki dir_fck ext _fck 46 32_mcko m/ s mcko 4632_ sdto ex t_mclk dir _bick d3v lvc d3v d3v cs n ccl k cdti pdn port3 rom 1 2 3 4 5 6 7 8 9 10 c5 5 0.1 u u2e 74hcu 04 11 10 u9 74l vc541 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 20 10 a1 a2 a3 a4 a5 a6 a7 a8 g1 g2 y1 y2 y3 y4 y5 y6 y7 y8 vcc gnd rp2 47k 6 5 4 3 2 1 7 u8 74l vc245 2 3 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 20 10 4 a1 a2 a4 a5 a6 a7 a8 dir g b1 b2 b3 b4 b5 b6 b7 b8 vcc gnd a3 u7 f 74hc04 13 12 c5 7 0. 1u r3 8 10k u7c 74 hc04 5 6 u1 1 74h c541 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 1 19 a1 y1 a2 y2 a3 y3 a4 y4 a5 y5 a6 y6 a7 y7 a8 y8 g1 g2 jp26 463 2_sdti r3 2 10 k u1 0d 74hc14 9 8 jp28 fck + c5 6 47u 1 2 u2 f 74hcu 04 13 12 sw 2 pdn 2 1 3 u2c 74hcu 04 5 6 jp29 bick_ inv r3 3 470 u7d 74hc04 9 8 r3 5 470 r3 7 470 u10 a 74hc14 1 2 u10 e 74hc14 11 10 r3 4 10 k c5 4 0. 1u u5e 74hc14 11 10 u5d 74hc14 9 8 u2d 74hcu 04 9 8 r3 9 10k r3 6 10 k jp30 sd ti u7e 74hc04 11 10 port4 ctrl 1 2 3 4 5 6 7 8 9 10 jp27 bick u10 f 74hc14 13 12 u7b 74 hc04 3 4 u1 0c 74hc14 5 6 d4 hsu11 9 k a u10 b 74hc14 3 4 rp3 47 k 6 5 4 3 2 1 7
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